An input buffer with opamp-based bootstrap circuit and cross-coupled substrate technique for 1.5-GS/s pipelined ADC in 40-nm CMOS process

This letter presents a high-linearity input buffer for RF sampling ADC. A common-source operational amplifier is added as a bootstrap circuit to mitigate the influence of channel-length modulation and current extracted by sampling circuits. A cross-coupled substrate technique is introduced to enhance the output impedance of tail current sources, thereby further improving linearity. The proposed input buffer is designed using a 40-nm CMOS process, consuming 60-mW under a 2.5-V supply, which can be applied in a 1.5-GS/s 14-bit pipelined ADC. Simulation results demonstrate that the input buffer achieves an SFDR/SNDR of 80.3/69.2 dB with a 1283-MHz input at 1.5-GS/s.