A 4ps Resolution Capacitive-Tuned Delay Pulse Shrinking Time to Digital Converter

被引：0

作者：

Tutuani, Patricia ^{[1
]}

Amankrah, Emmanuel ^{[1
]}

Geiger, Randall ^{[1
]}

机构：

[1] Iowa State Univ, Dept Elect & Comp Engn, Ames, IA 50011 USA

来源：

2024 IEEE 67TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, MWSCAS 2024 | 2024年

关键词：

Delay line; time-to-digital converter (TDC); Vernier Delay Line; Pulse Shrinking;

D O I：

10.1109/MWSCAS60917.2024.10658890

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a 12-bit Time-to-Digital Converter (TDC) that combines a pulse shrinking ring comprising an even number of inverting delay elements with a pulse-arbiter delay line. This innovative approach leverages the linearity of the pulse shrinking ring and the high-resolution capabilities of the pulse-arbiter delay line, resulting in a TDC with exceptional linearity and accuracy. With a resolution of 4ps, this TDC functions efficiently in a standard 0.18 mu m CMOS technology, offering a Full-Scale-Range (FSR) of 36600 ps.

引用

页码：1091 / 1095

页数：5

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