Adaptive Time-stepping Method for CMP Simulation Efficiency

被引:0
|
作者
Zhang, Rui [1 ]
Xie, Yu-wei [1 ]
Zhang, Qing [1 ]
Kan, Huan [2 ]
Pan, Wei-wei [2 ]
机构
[1] Semitronix Corp, Software Dept, Hangzhou, Peoples R China
[2] Semitronix Corp, Design Dept, Hangzhou, Peoples R China
关键词
DFM; CMP; BEOL; chip; dielectric; damascene process; yield; FFT; adaptive time steps;
D O I
10.1109/ISEDA62518.2024.10617641
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
As process technology scales down and new materials are introduced, coupled with the escalating complexity of processes, enhancing yield in chip production becomes an increasingly formidable task. The incorporation of an important process, Chemical Mechanical Polishing (CMP), is designed to ensure the controlled surface morphology of each wafer, thereby augmenting chip production yield. Building upon the findings of T. Tugbawa et al., the parameterization of layout pattern feature extraction, in conjunction with the modeling of corresponding process steps in chip production, allows us to simulate and predict the entire process of surface morphology changes during CMP. This paper introduces the development of modeling and prediction software for CMP simulation processes (CMPEXP), grounded in the aforementioned research. An adaptive time step iterative simulation strategy has been implemented in this study, resulting in an enhancement of simulation efficiency by approximately 150% compared to fixed time steps iteration.
引用
收藏
页码:587 / 591
页数:5
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