Design of GaN-on-Silicon Power-Rail ESD Clamp Circuit With Ultralow Leakage Current and Dynamic Timing-Voltage Detection Function

被引：0
|
作者：
Ke, Chao-Yang [1 ]
Ker, Ming-Dou [1 ]
机构：
[1] Natl Yang Ming Chiao Tung Univ, Inst Elect, Hsinchu 300, Taiwan
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2025年 / 72卷 / 03期
关键词：
Electrostatic discharges; Voltage; MODFETs; HEMTs; Leakage currents; Clamps; Transient analysis; Low voltage; Art; Resistors; Electrostatic discharge (ESD); enhancement-mode high electron mobility transistor (E-HEMT); ESD protection; GaN; HEMT; power-rail ESD clamp circuit;
D O I：
10.1109/TED.2025.3529405
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A power-rail electrostatic discharge (ESD) clamp circuit for monolithic GaN-based integrated circuits (ICs) with ultralow leakage current and dynamic timing-voltage detection function was proposed, which has been successfully verified in a 0.5-mu m GaN-on-Si process. The standby leakage current is only 0.8 nA. With the voltage detection, the proposed ESD clamp circuit can only be triggered by ESD events, and cannot be falsely triggered during fast power-on conditions. The experimental results demonstrate that the human-body-model (HBM) ESD robustness of the proposed design can be achieved over 6 kV. The triggered voltage of the ESD clamp circuit is flexible by adjusting the number of diode-connected high electron mobility transistors (HEMTs), so it can be utilized in different voltage ratings of V-cc.
引用
收藏
页码：1066 / 1074
页数：9
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