A PFM-Based Calibration Method for Low-Power High-Linearity Digital Pixel

The nonlinearity problem of digital pixels restricts the reduction in power consumption at the pixel-level circuit. The main cause of nonlinearity is discussed in this article and low power consumption is attained by reducing the static current in capacitive transimpedance amplifiers (CTIAs) and comparators. Linearity was successfully improved through the use of an off-chip calibration method. A 64 x 64 array prototype digital readout integrated circuit (DROIC) was fabricated using a 0.18 mu m 1P6M CMOS process. Experimental results indicated that the post-calibration linearity reached 99.6% with an input current of up to 1.5 mu A. The static power consumption per digital pixel was 6 mu W.