In-Memory Computing Architecture for Efficient Hardware Security

被引:0
|
作者
Ajmi, Hala [1 ]
Zayer, Fakhreddine [2 ]
Belgacem, Hamdi [1 ]
机构
[1] Electronics and Microelectronics Laboratory, Faculty of Sciences Of Monastir, University of Monastir, Monastir, Tunisia
[2] Khalifa University of Science and Technology, Khalifa Univesity, Abu Dhabi, United Arab Emirates
来源
关键词
Compilation and indexing terms; Copyright 2025 Elsevier Inc;
D O I
暂无
中图分类号
学科分类号
摘要
Digital storage - Hardware security - Integrated circuit design - Network security - Robots - Structural dynamics
引用
收藏
相关论文
共 50 条
  • [31] In-Memory Computing Based Hardware Accelerator Module for Deep Neural Networks
    Appukuttan, Allen
    Thomas, Emmanuel
    Nair, Harinandan R.
    Hemanth, S.
    Dhanaraj, K. J.
    Azeez, Maleeha Abdul
    2022 IEEE 19TH INDIA COUNCIL INTERNATIONAL CONFERENCE, INDICON, 2022,
  • [32] Hybrid In-memory Computing Architecture for the Training of Deep Neural Networks
    Joshi, Vinay
    He, Wangxin
    Seo, Jae-sun
    Rajendran, Bipin
    2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
  • [33] Multi-Objective Neural Architecture Search for In-Memory Computing
    Amin, Md Hasibul
    Mohammadi, Mohammadreza
    Zand, Ramtin
    2024 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, ISVLSI, 2024, : 343 - 348
  • [34] Special issue on in-memory computing: Circuits, system, architecture and verification
    Datta, Kamalika
    Drechsler, Rolf
    Memories - Materials, Devices, Circuits and Systems, 2023, 5
  • [35] Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture
    Wang, Xueyan
    Yang, Jianlei
    Zhao, Yinglin
    Jia, Xiaotao
    Yin, Rong
    Chen, Xuhang
    Qu, Gang
    Zhao, Weisheng
    IEEE TRANSACTIONS ON COMPUTERS, 2022, 71 (10) : 2462 - 2472
  • [36] Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge
    Rios, Marco
    Ponzina, Flavio
    Ansaloni, Giovanni
    Levisse, Alexandre
    Atienza, David
    PROCEEDINGS OF THE 32ND GREAT LAKES SYMPOSIUM ON VLSI 2022, GLSVLSI 2022, 2022, : 249 - 254
  • [37] Case Study on Integrated Architecture for In-Memory and In-Storage Computing
    Kim, Manho
    Kim, Sung-Ho
    Lee, Hyuk-Jae
    Rhee, Chae-Eun
    ELECTRONICS, 2021, 10 (15)
  • [38] An In-Memory-Computing Binary Neural Network Architecture With In-Memory Batch Normalization
    Rege, Prathamesh Prashant
    Yin, Ming
    Parihar, Sanjay
    Versaggi, Joseph
    Nemawarkar, Shashank
    IEEE ACCESS, 2024, 12 : 190889 - 190896
  • [39] A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing
    Sadredini, Elaheh
    Rahimi, Reza
    Verma, Vaibhav
    Stan, Mircea
    Skadron, Kevin
    IEEE COMPUTER ARCHITECTURE LETTERS, 2019, 18 (02) : 87 - 90
  • [40] DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm
    Lin, Chuan-Tung
    Wang, Dewei
    Zhang, Bo
    Chen, Gregory K.
    Knag, Phil C.
    Krishnamurthy, Ram Kumar
    Seok, Mingoo
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024, 59 (03) : 960 - 971