meet the requirements of the wreless communication industy, digital communication systems require increasingly advanced coding and modulatn technologies. Software- Defined Radio enables these advanced ideas to be easily adopted by such systems. The Finite Impulse Response filter is frequently used in wireless communication to pre-process detected signals to reduce noise by utilizing delay elements, multipliers, and adders. Traditional multiplier-based finite impulse response filter designs result in hardware-intensive multipliers that use a lot of space and energy and pose poor calculation speeds and low performance in throughput and latency. To overcome the existing issues, a novel Distributed Arithmetic with a Look Up Table-based FIR filter is proposed, which reduces the Bit Error Rate and latency and improves throughput by optimizing the channel equalizer as a crucial part of Software Defined Radio applications. Further, a key feature named the decimation factor is incorporated to dynamically alter the filter's output frequency response without altering the filter coefficients. Moreover, the worst-case critical route latency of partial product accumulation is reduced using a highly adaptable Parallel Prefix Adder. Additionally, the finite impulse response filters are integrated to decrease the number of Look-Up Tables, thereby saving time and memory. It also investigates the filter efficiency using faster multipliers and adders and validates it on an Artix-7 FPGA. As a result, the proposed model improved the filter's performance over the other existing designs by achieving an operating speed impro ed the filter's performance over the other of 260 MHz, delay of 190 ps, power dissipation of 1 mW and throughput of 938.12 Mbps with the number of Look-Up Tables being 16504.
