SELF-ALIGNED Mo-SILICIDE FORMATION.

被引：0
|
作者：
Nagasawa, Eiji
Okabayashi, Hidekazu
Morimoto, Mitsutaka
机构：
来源：
| 1600年 / 22期
关键词：
Compendex;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
MOLYBDENUM SILICON ALLOYS
引用
收藏
相关论文
共 50 条
  • [41] HIGH CONDUCTIVITY DIFFUSIONS AND GATE REGIONS USING SELF-ALIGNED SILICIDE TECHNOLOGY
    OSBURN, CM
    TSAI, MY
    ROBERTS, S
    LUCCHESE, CJ
    TING, CY
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1982, 129 (08) : C326 - C326
  • [42] Performance of a borosilica forming Mo-silicide coating in active oxidation environments
    Becker, J. R.
    Perepezko, J. H.
    CORROSION SCIENCE, 2025, 244
  • [43] A SELF-ALIGNED COBALT SILICIDE TECHNOLOGY USING RAPID THERMAL-PROCESSING
    VANDENHOVE, L
    WOLTERS, R
    MAEX, K
    DEKEERSMAECKER, R
    DECLERCK, G
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1986, 4 (06): : 1358 - 1363
  • [44] Self-aligned silicide gate GaN MISFETs with normally-off operation
    Taguchi, Shinya
    Hasegawa, Kazuya
    Nomoto, Kazuki
    Nakamura, Tohru
    PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 8, NO 7-8, 2011, 8 (7-8): : 2413 - 2415
  • [45] Self-Aligned Silicide Gate GaN MISFETs with Normally-Off Operation
    Taguchi, Shinya
    Hasegawa, Kazuya
    Nomoto, Kazuki
    Nakamura, Tohru
    REPORT OF RESEARCH CENTER OF ION BEAM TECHNOLOGY, HOSEI UNIVERSITY, SUPPL NO 29, 2011, 29 : 65 - 68
  • [46] TIW SILICIDE-GATE TECHNOLOGY FOR SELF-ALIGNED GAAS-FET
    GILL, SS
    PRYCE, GJ
    WOODWARD, J
    PHYSICA B & C, 1985, 129 (1-3): : 430 - 434
  • [47] THERMALLY STABLE, LOW-LEAKAGE SELF-ALIGNED TITANIUM SILICIDE JUNCTIONS
    YOSHIDA, T
    OGAWA, S
    OKUDA, S
    KOUZAKI, T
    TSUKAMOTO, K
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1990, 137 (06) : 1914 - 1917
  • [48] Investigation of a Self-Aligned Cobalt Silicide Process for Ohmic Contacts to Silicon Carbide
    Mattias Ekström
    Andrea Ferrario
    Carl-Mikael Zetterling
    Journal of Electronic Materials, 2019, 48 : 2509 - 2516
  • [49] Optimization of Ti and Co self-aligned silicide RTP for 0.10 μm CMOS
    Kittl, JA
    Hong, QZ
    Yang, H
    Yu, N
    Rodder, M
    Apte, PP
    Shiau, WT
    Chao, CP
    Breedijk, T
    Pas, MF
    ADVANCED INTERCONNECTS AND CONTACT MATERIALS AND PROCESSES FOR FUTURE INTEGRATED CIRCUITS, 1998, 514 : 255 - 260
  • [50] A self-aligned silicide process technology for sub-0.25 μm geometries
    White, TR
    Kolar, D
    Jahanbani, M
    Frisa, L
    Nagabushnam, R
    Chuang, H
    Tsui, P
    Cope, J
    Pulvirent, L
    Bolton, S
    MICROELECTRONIC DEVICE TECHNOLOGY II, 1998, 3506 : 112 - 119
12345