High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies

被引：0
|
作者：
Allam, Mohamed W. [1 ]
Anis, Mohab H. [1 ]
Elmasry, Mohamed I. [1 ]
机构：
[1] Univ of Waterloo, Waterloo, Ont, Canada
来源：
Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers | 2000年
关键词：
Formal logic - Logic design - Spurious signal noise;
D O I：
10.1109/lpe.2000.155270
中图分类号：
学科分类号：
摘要：
A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-off between performance and noise margins in conventional CD-Domino logic while dissipating low dynamic power with minimal area overhead. A dual-threshold (MTCMOS) implementation of HS-Domino and DDCVS logic is also devised. This implementation achieves low leakage values during standby, while maintaining high performance and low dynamic power during the active mode.
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页码：155 / 160
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