USE OF CORE™ IN THE SYSTEM ENGINEERING OF AN ANALOG ASIC

被引：0
|
作者：
Gardner, John R. [1 ]
机构：
[1] Textron Systems Division, 201 Lowell Street, Wilmington,MA,01887, United States
来源：
INCOSE International Symposium | 1996年 / 6卷 / 01期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：360 / 364
相关论文
共 50 条
  • [31] Low-Noise Analog ASIC for Silicon and CdTe Sensors
    Kishishita, Tetsuichi
    Sato, Goro
    Ikeda, Hirokazu
    Takahashi, Tadayuki
    Kiyuna, Tatsuya
    Mito, Yoshio
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2010, 57 (05) : 2971 - 2977
  • [32] Comparative Study on Cascade Control Configuration in Engineering Phase for Analog System and FF System
    Khochasin, Narupon
    Trisuwannawat, Thanit
    Julsereewong, Prasit
    Julsereewong, Amphawan
    2016 IEEE/SICE INTERNATIONAL SYMPOSIUM ON SYSTEM INTEGRATION (SII), 2016, : 881 - 886
  • [33] Use of System Engineering in Modern Metrology
    YANG Shiyuan(Hefei University of Technology
    Journal of Systems Science and Systems Engineering, 1995, (01) : 90 - 96
  • [34] Performance of an Analog ASIC Developed for X-ray CCD Camera Readout System Onboard Astronomical Satellite
    Nakajima, Hiroshi
    Matsuura, Daisuke
    Anabuki, Naohisa
    Miyata, Emi
    Tsunemi, Hiroshi
    Doty, John P.
    Ikeda, Hirokazu
    Takashima, Takeshi
    Katayama, Haruyoshi
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009, 56 (03) : 747 - 751
  • [35] Analog front-end ASIC requirements for a FDM broadband powerline system enabling co-existence
    Bauwelinck, J.
    De Backer, E.
    Melange, C.
    Qiu, X. Z.
    Vandewege, J.
    Thornton, C.
    Boss, A.
    Horvath, S.
    Rao, S.
    2007 IEEE INTERNATIONAL SYMPOSIUM ON POWER LINE COMMUNICATIONS AND ITS APPLICATIONS, 2007, : 436 - +
  • [36] ASIC embedded programmable gate array core (EPGAT)
    Tanurhan, Y
    ELECTRONIC ENGINEERING, 2001, 73 (891): : 87 - +
  • [37] Speed optimized ASIC turbo decoder core design
    Chen, XY
    Yao, QD
    Liu, P
    APOC 2003: ASIA-PACIFIC OPTICAL AND WIRELESS COMMUNICATIONS; WIRELESS COMMUNICATIONS AND NETWORKS, 2003, 5284 : 214 - 220
  • [38] ALTERABLE RISC CORE FINE TUNES ASIC ARCHITECTURE
    BURSKY, D
    ELECTRONIC DESIGN, 1993, 41 (03) : 92 - &
  • [39] Design of miniaturized terahertz camera core based on ASIC
    Zhang, Yunkui
    Liu, Dexing
    Shi, Jiaxin
    Cai, Ming
    Wang, Jun
    SIXTH SYMPOSIUM ON NOVEL OPTOELECTRONIC DETECTION TECHNOLOGY AND APPLICATIONS, 2020, 11455
  • [40] Integration of a RISC processor core into a disk controller ASIC
    Ou, Michael
    Ramlaoui, Hussam
    Electronic Engineering (London), 1997, 69 (849): : 41 - 42
12345