PARITY CHECKER/GENERATOR.

被引：0
|
作者：
Torres, A.
机构：
来源：
IBM technical disclosure bulletin | 1984年 / 27卷 / 4 A期
关键词：
COMPUTERS; MICROPROCESSOR;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Parity checking of data in microprocessor storage channels typically requires a number of logic levels. The invention represents a method for generating a parity error signal for 36 bits utilizing only four logic levels and possibly only three logic levels (depending on polarity configuration).
引用
收藏
页码：1889 / 1892
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