COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR STRUCTURE WITH TRENCH ISOLATION.

被引：0
|
作者：
Chesebro, D.G.
El-Kareh, B.
机构：
来源：
IBM technical disclosure bulletin | 1984年 / 27卷 / 05期
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D O I：
暂无
中图分类号：
TN [电子技术、通信技术];
学科分类号：
0809 ;
摘要：
A complementary metal-oxide-semiconductor (CMOS) structure is provided which uses trench isolation refilled with polyimide that inhibits latch up. The structure includes an N type semiconductor substrate with an implanted P type pocket. Alternatively, an N plus substrate may be used on which an N type silicon layer is epitaxially grown.
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