KDSS - 1. A DISCRETE SYSTEM SIMULATOR BASED ON DATA DRIVEN ARCHITECTURE.

A description is given of a parallel processing procedure and its implementation for a discrete system simulator based on a data driven parallel processing architecture. Specifically the distributed time-management between units of parallel processing, QSV processors, the concepts of nonempty and empty packets, a synchronization mechanism for data transmission using 2 bit flags and distributed synchronous algorithms using packets are explained from the viewpoint of parallel processing. A report is given on the first experimental machine KDSS-1 which can handle more than 100 parallel processing units of QSV processors. Due to special attention given to the interface design, because of expected difficulty, a new interconnection method in which 64 processing units can read out completely in parallel, has been proven to be an effective interconnection method in fields requiring multiinput-multioutput interconnections and high data transmission ability.