Configurable and reconfigurable computing for digital signal processing

被引:0
|
作者
Sueyoshi, Toshinori [1 ]
Iida, Masahiro [1 ]
机构
[1] Dept. of Computer Science, Faculty of Engineering, Kumamoto University, Kumamoto-shi, 860-8555, Japan
关键词
D O I
暂无
中图分类号
学科分类号
摘要
Digital signal processing
引用
收藏
页码:591 / 599
相关论文
共 50 条
  • [31] How can DNA computing be applied to digital signal processing?
    Tsaftaris, SA
    Katsaggelos, AK
    Pappas, TN
    Papoutsakis, ET
    IEEE SIGNAL PROCESSING MAGAZINE, 2004, 21 (06) : 57 - 61
  • [32] Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing
    Angizi, Shaahin
    He, Zhezhi
    DeMara, Ronald F.
    Fan, Deliang
    PROCEEDINGS OF THE EIGHTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2017, : 391 - 396
  • [33] Configurable computing and sonar processing - Architectures and implementations
    Nelson, BE
    CONFERENCE RECORD OF THE THIRTY-FIFTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, VOLS 1 AND 2, 2001, : 56 - 60
  • [34] A reconfigurable digital signal processor
    Tan, BK
    Ogawa, T
    Yoshimura, R
    Taniguchi, K
    IEICE TRANSACTIONS ON ELECTRONICS, 1998, E81C (09): : 1424 - 1430
  • [35] Dynamically reconfigurable dataflow architecture for high-performance digital signal processing
    Voigt, S.
    Baesler, M.
    Teufel, T.
    JOURNAL OF SYSTEMS ARCHITECTURE, 2010, 56 (11) : 561 - 576
  • [36] Run-time reconfigurable systems for digital signal processing applications: A survey
    Shoa, A
    Shirani, S
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2005, 39 (03): : 213 - 235
  • [37] Parallelisation of digital signal processing in uniform and reconfigurable filter banks for satellite communications
    Gockler, Heinz G.
    Groth, Alexandra
    Abdulazim, Mohammed N.
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 1059 - +
  • [38] Reconfigurable pipelined 2-D convolvers for fast digital signal processing
    Bosi, B
    Bois, G
    Savaria, Y
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1999, 7 (03) : 299 - 308
  • [39] Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
    Alireza Shoa
    Shahram Shirani
    Journal of VLSI signal processing systems for signal, image and video technology, 2005, 39 : 213 - 235
  • [40] A novel architecture of dynamically reconfigurable fused multiply–adder for digital signal processing
    Tsukahara A.
    Kanasugi A.
    Artificial Life and Robotics, 2014, 19 (3) : 233 - 238