NEW APPROACH TO THE REALIZATION OF LOW-SENSITIVITY IIR DIGITAL FILTERS.

被引：92
|
作者：
Vaidyanathan, P.P. [1 ]
Mitra, Sanjit K. [1 ]
Neuvo, Yrjoe [1 ]
机构：
[1] California Inst of Technology,, Pasadena, CA, USA, California Inst of Technology, Pasadena, CA, USA
来源：
IEEE Transactions on Acoustics, Speech, and Signal Processing | 1986年 / ASSP-34卷 / 02期
关键词：
D O I：
10.1109/TASSP.1986.1164829
中图分类号：
学科分类号：
摘要：
37
引用
收藏
页码：350 / 361
相关论文
共 50 条
  • [31] Methods to design low-sensitivity canonical digital filters using impulse response data
    DeBrunner, VE
    Tutunji, TA
    Corzine, AR
    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 2, 1996, : 397 - 400
  • [32] FINITE STATE MACHINE REALIZATION OF IIR DIGITAL-FILTERS
    YAN, ZZ
    YU, FY
    IEEE INTERNATIONAL CONFERENCE ON SYSTEMS ENGINEERING ///, 1989, : 387 - 390
  • [33] Reference networks for simultaneous realization of complex IIR digital filters
    Okabayashi, K
    Takahashi, S
    1997 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS 1 AND 2: PACRIM 10 YEARS - 1987-1997, 1997, : 165 - 168
  • [34] Pole-Position Sensitivity of Wave Digital Filters.
    Wisliceny, Johann
    Zeitschrift fur Elektrische Informations - und Energietechnik, 1977, 7 (03): : 272 - 279
  • [35] LOW-SENSITIVITY SECOND-ORDER DIGITAL FILTERS - ANALYSIS AND DESIGN IN TERMS OF FREQUENCY SENSITIVITY.
    Nishihara, Akinori
    Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E, 1984, E 67 (08): : 433 - 439
  • [36] Analysis and Minimization of l2-Sensitivity for Block-State Realization of IIR Digital Filters
    Doi, Akimitsu
    Hinamoto, Takao
    Lu, Wu-Sheng
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2018, E101A (02): : 447 - 459
  • [37] BLOCK EXTRACTION APPROACH TO REALIZATION OF SWITCHED-CAPACITOR FILTERS.
    Nishimura, S.
    Fujii, S.
    Li, L.Y.
    Hirano, K.
    Memoirs of the Faculty of Engineering, Kobe University, 1982, (28): : 273 - 283
  • [38] Two-type-interlaced structure and LBR test for low-sensitivity digital filter realization
    LG Electronics Research Cent, Seoul, Korea, Republic of
    IEEE Trans Circuits Syst II Analog Digital Signal Process, 7 (473-477):
  • [39] Low-sensitivity IIR switched-capacitor decimation filters using delay lines with staggered T/H stages
    Petraglia, A
    Pereira, JS
    Barúgui, FAP
    IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2006, 153 (02): : 193 - 198
  • [40] LOW-SENSITIVITY SWITCHED-CAPACITOR LADDER FILTERS
    LEE, MS
    CHANG, C
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1980, 27 (06): : 475 - 480
12345