共 50 条
- [31] CMOS Scaling for sub-90 nm to sub-10 nm 17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 30 - 35
- [33] Sub-10 nm silicon FinFET devices on SOI substrate made by block copolymer lithography 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 21 - 23
- [34] 0.1-nanometer resolution positioning stage for sub-10 nm scanning probe lithography ALTERNATIVE LITHOGRAPHIC TECHNOLOGIES V, 2013, 8680
- [37] Multifield sub-5nm overlay in imprint lithography JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2016, 34 (06):
- [38] Sub-10 nm Carbon Nanotube Transistor 2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,
- [40] Challenges of SEM metrology at sub-10 nm METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XXVI, PTS 1 AND 2, 2012, 8324