High-performance active adder

被引：0
|
作者：
Seixas, J.M. [1 ]
Cerqueira, A.S. [1 ]
Caloba, L.P. [1 ]
机构：
[1] COPPE/EE/UFRJ, Rio de Janeiro, Brazil
来源：
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems | 1998年 / 1卷
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：377 / 380
相关论文
共 50 条
  • [31] Design and implementation of high-performance 20-T hybrid full adder circuit
    Kandpal, Jyoti
    Tomar, Abhishek
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2024, 119 (01) : 97 - 110
  • [32] Design and implementation of ternary adder for High-Performance arithmetic applications by using CNTFET material
    Panwar, Uday
    Sharma, Parul
    MATERIALS TODAY-PROCEEDINGS, 2022, 63 : 773 - 777
  • [33] HIGH-PERFORMANCE FPGA-BASED FLOATING-POINT ADDER WITH THREE INPUTS
    Guntoro, Andre
    Glesner, Manfred
    2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2, 2008, : 626 - 629
  • [34] Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs
    Roy, Subhendu
    Choudhury, Mihir
    Puri, Ruchir
    Pan, David Z.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (05) : 820 - 831
  • [35] Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs
    Roy, Subhendu
    Choudhury, Mihir
    Puri, Ruchir
    Pan, David Z.
    2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2015, : 249 - 254
  • [36] A HIGH-PERFORMANCE (AL,GA)AS/GAAS MODFET BUTTERFLY ADDER CHIP FOR FFT COMPUTATION
    AKINWANDE, AI
    BETZ, BK
    MACTAGGART, IR
    GRIDER, DE
    NARUM, DH
    LANGE, TH
    NOHAVA, TE
    NOHAVA, JC
    TETZLAFF, D
    ARCH, DK
    GAAS IC SYMPOSIUM /: TECHNICAL DIGEST 1989, 1989, : 53 - 56
  • [37] A novel high-performance CMOS 1-bit full-adder cell
    Shams, AM
    Bayoumi, MA
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2000, 47 (05) : 478 - 481
  • [38] High-Performance 10-Transistor Adder Cell for Low-Power Applications
    Misra, Aishani
    Birla, Shilpi
    Singh, Neha
    Dargar, Shashi Kant
    IETE JOURNAL OF RESEARCH, 2023, 69 (11) : 8318 - 8336
  • [39] A high-performance full swing 1-bit hybrid full adder cell
    Hussain, Shahbaz
    Hasan, Mehedi
    Agrawal, Gazal
    Hasan, Mohd
    IET CIRCUITS DEVICES & SYSTEMS, 2022, 16 (03) : 210 - 217
  • [40] Mixed Full Adder topologies for high-performance low-power arithmetic circuits
    Alioto, M.
    Di Cataldo, G.
    Palumbob, G.
    MICROELECTRONICS JOURNAL, 2007, 38 (01) : 130 - 139
12345