Switch-level test generation system for synchronous and asynchronous circuits

In the developed switch-level system for synchronous and asynchronous circuits, a new algorithm for fully automatic switch-level test generation and an existing fault simulator are integrated. For synchronous circuits, the time-frame based algorithm employs asynchronous processing within each clock phase to model the passage of time. In asynchronous circuits, the algorithm uses asynchronous processing to reach stability within and between modules. The test generators presented utilizes the monotonicity of the logic network to speed up the search for a solution. Results obtained in benchmark circuits show that the test generator outperforms an existing switch-level test generator both in time and space requirements. The algorithm is suitable for mixed-level test generation.