A RISC architecture for symbolic computation

被引：0
|
作者：
Kieburtz, Richard B. [1 ]
机构：
[1] Oregon Graduate Center, 19600N.W. von Neumann Dr., Beaverton,OR,97006, United States
来源：
Operating Systems Review (ACM) | 1987年 / 21卷 / 04期
关键词：
Cache memory - Directed graphs - Pipeline processing systems - Reduced instruction set computing;
D O I：
10.1145/36204.36197
中图分类号：
学科分类号：
摘要：
The G-machine is a language-directed processor architecture designed to support graph reduction as a model of computation. It can carry out lazy evaluation of functional language programs and can evaluate programs in which logical variables are used. To support these language features, the abstract machine requires tagged memory and executes some rather complex instructions, such as to evaluate a function application.This paper explores an implementation of the G-machine as a high performance RISC architecture. Complex instructions can be represented by RISC code without experiencing a large expansion of code volume. The instruction pipeline is discussed in some detail. The processor is intended to be integrated into a standard, 32-bit memory architecture. Tagged memory is supported by aggregating data with tags in a cache. © 1987 Copyright is held by the owner/author(s).
引用
收藏
页码：146 / 155
相关论文
共 50 条
  • [21] 88000-RISC ARCHITECTURE
    MELEAR, C
    CA-DSP 89, VOLS 1 AND 2: 1989 INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING, 1989, : S47 - S55
  • [22] RISC architecture gets an upgrade
    Cravotta, R
    EDN, 2001, 46 (26) : 22 - 22
  • [23] Symbolic architecture
    Santacesaria, Marco
    Industria Italiana del Cemento, 2002, 72 (JUN.): : 510 - 523
  • [24] CHOOSING THE RIGHT RISC ARCHITECTURE
    WILLENZ, A
    BOUREKAS, P
    HIGH PERFORMANCE SYSTEMS-THE MAGAZINE FOR TECHNOLOGY CHAMPIONS, 1990, 11 (03): : 42 - &
  • [25] A novel 32 bit RISC architecture unifying RISC and DSP
    Baumhof, C
    Muller, F
    Muller, O
    Schlett, M
    1997 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I - V: VOL I: PLENARY, EXPERT SUMMARIES, SPECIAL, AUDIO, UNDERWATER ACOUSTICS, VLSI; VOL II: SPEECH PROCESSING; VOL III: SPEECH PROCESSING, DIGITAL SIGNAL PROCESSING; VOL IV: MULTIDIMENSIONAL SIGNAL PROCESSING, NEURAL NETWORKS - VOL V: STATISTICAL SIGNAL AND ARRAY PROCESSING, APPLICATIONS, 1997, : 587 - 590
  • [26] RISC ARCHITECTURE IN TRANSPUTERS AND TRANSPUTER ARRAYS
    HEY, AJG
    COMPUTER PHYSICS COMMUNICATIONS, 1988, 50 (1-2) : 23 - 31
  • [27] RISC ARCHITECTURE - A PERSPECTIVE ON THE PAST AND FUTURE
    HENNESSY, J
    ADVANCED RESEARCH IN VLSI : PROCEEDINGS OF THE DECENNIAL CALTECH CONFERENCE ON VLSI, 1989, : 37 - 42
  • [28] Factor Varieties and Symbolic Computation
    Salibra, Antonino
    Manzonetto, Giulio
    Favro, Giordano
    PROCEEDINGS OF THE 31ST ANNUAL ACM-IEEE SYMPOSIUM ON LOGIC IN COMPUTER SCIENCE (LICS 2016), 2016, : 739 - 748
  • [29] Symbolic computation in control theory
    Giorgadze, G
    CCCT 2003, VOL 5, PROCEEDINGS: COMPUTER, COMMUNICATION AND CONTROL TECHNOLOGIES: II, 2003, : 100 - 101
  • [30] SYMBOLIC COMPUTATION FOR WITT RINGS
    JUOZAPAVICIUS, A
    LECTURE NOTES IN COMPUTER SCIENCE, 1989, 358 : 271 - 273
12345