LOW COST HIERARCHICAL SYSTEM FOR VLSI LAYOUT AND VERIFICATION.

被引：0
|
作者：
Edmondson, Tom H.
Jennings, Richard M.
机构：
来源：
Proceedings - Design Automation Conference | 1981年
关键词：
Compendex;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Integrated circuits
引用
收藏
页码：505 / 510
相关论文
共 50 条
  • [1] AUTOMATIC VLSI LAYOUT VERIFICATION.
    Williams, Laurin
    Proceedings - Design Automation Conference, 1981, : 726 - 732
  • [2] Logic-to-logic comparator for VLSI layout verification.
    Maurer, Peter M.
    Schapira, Alexander D.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988, 7 (06) : 897 - 907
  • [3] SHARPS: A HIERARCHICAL LAYOUT SYSTEM FOR VLSI.
    Chiba, Toru
    Okuda, Noboru
    Kambe, Takashi
    Nishioka, Ikuo
    Inufushi, Tsuneo
    Kimura, Seiji
    Proceedings - Design Automation Conference, 1981, : 820 - 827
  • [4] CONSIDERATIONS ON A VLSI ORIENTED CASE STUDY FOR INTEGRATED SYSTEM DESIGN VERIFICATION.
    Ichiko, Takao
    NEC Research and Development, 1985, (76): : 1 - 8
  • [5] HIERARCHICAL LAYOUT VERIFICATION
    WAGNER, TJ
    IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (01): : 31 - 37
  • [6] SYSTEM IDENTIFICATION: AN EXPERIMENTAL VERIFICATION.
    Ciskowski, R.D.
    Liu, C.H.
    Ottesen, H.H.
    Rahman, S.U.
    1600, (31):
  • [7] Parallel Algorithms for VLSI Layout Verification
    Journal of Parallel and Distributed Computing, 36 (02):
  • [8] Parallel algorithms for VLSI layout verification
    MacPherson, K
    Banerjee, P
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 1996, 36 (02) : 156 - 172
  • [9] Hierarchical VLSI layout circuit extraction
    Zeng, Xian-Qiang
    Chen, Hou-Peng
    0
    Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design & Computer Graphics, 1998, 10 (Suppl): : 101 - 105
  • [10] RULE-BASED VLSI VERIFICATION SYSTEM CONSTRAINED BY LAYOUT PARASITICS
    WENIN, J
    VANCAMP, M
    VERHASSELT, J
    LEONARD, J
    GUEBELS, P
    26TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, 1989, : 662 - 667
12345