Development of three-dimensional integration technology for highly parallel image-processing chip

被引：0
|
作者：
Lee, Kang Wook [4 ]
Nakamura, Tomonori [4 ]
Sakuma, Katsuyuki [4 ]
Park, Ki Tae [4 ]
Shimazutsu, Hiroaki [1 ]
Miyakawa, Nobuaki [2 ]
Kim, Ki Yoon [3 ]
Kurino, Hiroyuki [4 ]
Koyanagi, Mitsumasa [4 ]
机构：
[1] Research Center, Mitsubishi Heavy Co., Hiroshima 733-8553, Japan
[2] Advanced Technology Center, Fuji Xerox Co., Kanagawa 243-04, Japan
[3] Japan Sci. and Technol. Corp.(CREST), Tokyo 101-0032, Japan
[4] Dept. Mach. Intell. and Syst. Eng., Tohoku University, 01 Aza-Aoba Aramaki, Aoba-ku, Sendai 980-8579, Japan
来源：
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 2000年 / 39卷 / 5 B期
关键词：
Three dimensional integration - Wafer level bonding;
D O I：
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中图分类号：
学科分类号：
摘要：
引用
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页码：2473 / 2477
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