FLEXIBLE ARCHITECTURE FOR CHEAP NUMBER CRUNCHING.

Some of the key design features of the AP400 array processor are described, which keep the hardware busy without burdening the user. These include putting the control of pipelined arithmetics into hardware, and incorporating FIFO buffering to direct operations with the convenience of minicomputer type software. The AP400's control processor has RAM program memory, 16 general purpose registers, 8 levels of hardware vectored interrupts, and a short, vertically-oriented word format. Execution speed is sufficient to allow the same control processor to handle the executive software burden as well as command the arithmetics and the interface.