HIGH PERFORMANCE TWIN-CELL MEMORY ARRAY.

被引：0

作者：

Scheuerlein, R.E.

Walker, W.W.

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来源：

IBM technical disclosure bulletin | 1984年 / 26卷 / 09期

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摘要：

In a twin-cell memory array where signals are stored in potential wells, the time required for sensing is considerably shortened by providing a substantially zero threshold voltage device between adjacent potential storage wells, which avoids cell position sensitivity. It is shown that by discharging unselected word lines to ground potential and allowing them to float, information stored in the cells along the unselected word lines is prevented from being disturbed.

引用

页码：4525 / 4527

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