Analysis, estimation and reduction of simultaneous switching noise

被引:0
|
作者
Abderrahman, A. [1 ]
Savaria, Y. [1 ]
Kaminska, B. [1 ]
机构
[1] Ecole Polytechnique de Montreal, Montreal, Canada
关键词
D O I
暂无
中图分类号
学科分类号
摘要
(Edited Abstract)
引用
收藏
页码:133 / 143
相关论文
共 50 条
  • [41] Simultaneous Switching Noise Analysis of Reference Voltage Rails for Pseudo Differential Interfaces
    Park, Sung Joo
    Choi, Jae Young
    Swaminathan, Madhavan
    2012 IEEE 21ST CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2012, : 47 - 50
  • [42] Modeling and Analysis of Simultaneous Switching Noise for Full Wafer Scale Chip Core
    Kim, Hyunwoo
    Choi, Seonguk
    Park, Joonsang
    Kim, Haeyeon
    Son, Kceyoung
    Lee, Junghyun
    Yoon, Jiwon
    Hong, Jonghyun
    Sim, Boogyo
    Kim, Keunwoo
    Shin, Tacit'
    Kim, Joungho
    2023 IEEE 32ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, EPEPS, 2023,
  • [43] Design and analysis of a novel Electromagnetic Bandgap structure for suppressing simultaneous switching noise
    Lu, Hong Min
    Zhao, J.X.
    Yu, Z.Y.
    Progress In Electromagnetics Research C, 2012, 30 : 81 - 91
  • [44] Estimation of the Noise Variance in Image and Noise Reduction
    Kim, Yeong-Hwa
    Nam, Jiho
    KOREAN JOURNAL OF APPLIED STATISTICS, 2011, 24 (05) : 905 - 914
  • [45] An Adaptive On-chip ESR Controller Scheme in Power Distribution Network for Simultaneous Switching Noise Reduction
    Shim, Jongjoo
    Shin, Minchul
    Kim, Hyungsoo
    Kim, Yongju
    Park, Kunwoo
    Cho, Jeonghyeon
    Kim, Joungho
    2008 IEEE-EPEP ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2008, : 157 - +
  • [46] Significant reduction of power/ground inductive impedance and simultaneous switching noise by using embedded film capacitor
    Kim, H
    Jeong, Y
    Park, J
    Lee, S
    Hong, J
    Hong, Y
    Kim, J
    ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2003, : 129 - 132
  • [47] S-parameter based technique for simultaneous switching noise analysis in electronic packages
    Jin, Z
    Iyer, MK
    Qiu, YL
    Ooi, BL
    Leong, MS
    IEEE TRANSACTIONS ON ADVANCED PACKAGING, 1999, 22 (03): : 267 - 273
  • [48] An Analysis of the Timing Behavior of CMOS Digital Blocks under Simultaneous Switching Noise Conditions
    Azais, F.
    Bertrand, Y.
    Renovell, M.
    PROCEEDINGS OF THE 2009 IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2009, : 158 - 163
  • [50] Simultaneous switching noise in FPGA and structure ASIC devices, methodologies for analysis, modeling, and validation
    Shi, Hong
    Liu, Geping
    Liu, Alan
    Pannikkat, Anil
    Ng, Kok Siang
    Yew, Yee Huan
    56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, : 229 - +