PARALLEL PROCESSING SCHEME FOR AN ITERATIVE IF STATEMENT ON A MULTIPROCESSOR SYSTEM.

被引：0
|
作者：
Marushima, Toshikazu [1 ]
Muraoka, Yoichi [1 ]
机构：
[1] Waseda Univ, Jpn, Waseda Univ, Jpn
来源：
Bulletin of Centre for Informatics (Waseda University) | 1600年 / 3卷
关键词：
CIRCULAR REFERENCES - ITERATIVE IF STATEMENT - LOOPS - PIPELINED VECTOR-PROCESSOR;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
(Edited Abstract)
引用
收藏
页码：76 / 79
相关论文
共 50 条
  • [41] Analysis of the Effect of Hardware Conflicts on Efficiency of a Multiprocessor System.
    Berezkin, A.K.
    Trudy LPI, 1983, (391): : 56 - 59
  • [42] Parallel image processing using a Pentium based shared-memory multiprocessor-system
    Rothlubbers, C
    Orglmeister, R
    PARALLEL AND DISTRIBUTED METHODS FOR IMAGE PROCESSING, 1997, 3166 : 46 - 54
  • [43] Hardware design in statement level parallel processing
    Shimoo, K
    Yamawaki, A
    Iwane, M
    PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGY, 2004, : 317 - 320
  • [44] Parallel and multiprocessor vision system architectures - Preface
    Bourbakis, NG
    INTERNATIONAL JOURNAL OF PATTERN RECOGNITION AND ARTIFICIAL INTELLIGENCE, 1998, 12 (03) : 263 - 264
  • [45] Effective implementation of a parallel software on a multiprocessor system
    Tayel, Mazhar
    Ahmed, Mohammed Gamal Eldin
    National Radio Science Conference, NRSC, Proceedings, 1998,
  • [46] A Novel Multiprocessor Architecture For Massively Parallel System
    Khan, Zaki Ahmad
    Siddiqui, Jamshed
    Samad, Abdus
    2014 INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED AND GRID COMPUTING (PDGC), 2014, : 466 - 471
  • [47] AN EXPERIMENTAL MULTIPROCESSOR SYSTEM FOR DISTRIBUTED PARALLEL COMPUTATIONS
    DEMAEYER, L
    DINICOLA, A
    MAETCHE, R
    VONDERMALSBURG, C
    WISKOTT, L
    MICROPROCESSING AND MICROPROGRAMMING, 1990, 26 (05): : 305 - 317
  • [48] COMPUTATION OF MULTIBODY SYSTEM DYNAMICS BY A MULTIPROCESSOR SCHEME
    ZHENG, YF
    HEMAMI, HS
    IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS, 1986, 16 (01): : 102 - 110
  • [49] PARALLEL PIPELINE MULTIPROCESSOR ARCHITECTURES FOR SAR DATA-PROCESSING
    ALBRIZIO, R
    MAZZONE, A
    VENEZIANI, N
    ALOISIO, G
    EUROPEAN TRANSACTIONS ON TELECOMMUNICATIONS, 1991, 2 (06): : 635 - 642
  • [50] Multigrain parallel processing for JPEG encoding on a single chip multiprocessor
    Kodaka, T
    Kimura, K
    Kasahara, H
    INTERNATIONAL WORKSHOP ON INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS, 2002, : 57 - 63
12345