LOOK TO ASYNCHRONOUS SEQUENTIAL LOGIC.

A self-clocked feature of a new asynchronous sequential logic design approach makes designing as simple as the conventional synchronous approach. An internal clock is generated when input changes occur. The clock pulse then drives edge-clocked flip-flops that change the state. In this sense internal operation is similar to that of synchronous systems. This overcomes the traditional asynchronous problems of races, hazards and the need to assign extra external states to combat them. In addition there needn't be any restrictions against multiple-input changes. Fast response is achieved because the circuit does not wait for a clock edge. With CMOS, power is conserved because there is no external clock and hence no rapid dissipation of power. Also CMOS requires low standby power because when the inputs don't change, all circuitry is quiescent.