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- [32] ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration PROCEEDINGS OF THE 2001 8TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2001, : 85 - 90
- [37] A technology-independent CAD tool for ESD protection device extraction - ESDExtractor IEEE/ACM INTERNATIONAL CONFERENCE ON CAD-02, DIGEST OF TECHNICAL PAPERS, 2002, : 510 - 513