Design and implementation of Gbps VLSI architecture of the cipher engine orienting to IEEE 802.11ac

In this paper, the implementation of multiple security protocols for IEEE 802.11i was researched. A very large scale integration (VLSI) architecture of the multi-mode cipher engine supporting WEP/TKIP/CCMP protocols was presented taking into account the demand for high throughput of the next generation wireless local area network (WLAN) system that is represented by IEEE 802.11ac. A key searching algorithm based on Hash scheme was proposed to reduce the lookup clock latency. For the high throughput hardware implementation of advanced encryption standard (AES) algorithm, composite field arithmetic was employed. In order to improve the data throughput and reduce the response time, dual AES computing core with parallel structure was used to implement the cipher block chaining message authentication code (CCM) mode. The proposed design was implemented in both FPGA and ASIC. The results show that the cipher engine with reconfiguration architecture can achieve 33 clock cycles, and the computing throughput is 3.747 Gbit/s when the work frequency is 322 MHz. ©, 2015, Editorial Board of Journal of HEU. All right reserved.