共 50 条
- [11] An Ultra-Dense Irradiation Test Structure with a NAND/NOR Readout Chain for Characterizing Soft Error Rates of 14nm Combinational Logic Circuits 2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2017,
- [14] Logic-In-Memory: A NanoMagnet Logic Implementation 2015 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2015, : 286 - 291
- [16] Collaborative Error Control Method for Sequential Logic Circuits 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 785 - 788
- [17] Probabilistic Maximum Error Modeling for Unreliable Logic Circuits GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, 2007, : 223 - 226
- [18] Fast Error Aware Model for Arithmetic and Logic Circuits 2012 IEEE 30TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2012, : 322 - 328
- [20] Logic synthesis of multilevel circuits with concurrent error detection IEEE Trans Comput Aided Des Integr Circuits Syst, 7 (783-789):