Silicon complementary metal-oxide-semiconductor field-effect transistors with dual work function gate

被引：0

作者：

Na, Kee-Yeol ^{[1
]}

Kim, Yeong-Seuk ^{[1
]}

机构：

[1] Dept. of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk 361-763, Korea, Republic of

来源：

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 2006年 / 45卷 / 12期

关键词：

This paper discusses silicon complementary metal-oxide-semieonductor (CMOS) field-effect transistors with dual work function gates (DWFG) to improve transconductance (gm) and drain conductance (gds) characteristics. For a n-channel metaloxide-semiconductor field-effect transistor (MOSFET) device; the polycrystalline silicon (poly-Si) gate on the source and drain side are doped p+ and n+; respectively and vice versa for a p-channel MOSFET. The work function difference in a poly-Si gate affects channel potential distribution and increases the lateral electric field inside the channel. The increased electric field inside the channel improves carrier drift velocity. Experimental results from the fabricated DWFG devices show improved gm and gds over conventional single work function gate devices. © 2006 The Japan Society of Applied Physics;

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学科分类号：

摘要：

Journal article (JA)

引用

页码：9033 / 9036

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