A novel low-energy half-select-free 9T SRAM cell based on CNTFETs with enhanced write performance

This work proposes a novel 9 T SRAM cell based on carbon nanotube field-effect transistors (CNTFETs). The design features an innovative writing technique, leveraging a floating method to write a '1 ' into the cell, significantly enhancing writing ability. Including row and column-based control signals ensures that data in halfselected cells remains stable during operations. The read operation is optimized for energy efficiency using only a single CNTFET. The symmetric structure of the proposed design, utilizing four inverters and a single transistor for the read operation, minimizes the overall overhead compared to 9 T SRAM cells. The results demonstrate that the proposed design achieves a 24 % improvement in write stability and reduces overall energy consumption for both read and write operations compared to existing SRAM cell designs. The energy consumption of the proposed design during read and write operations is approximately 93.7 % and 30 % lower, respectively than that of the compared designs at a supply voltage of 0.6 V. Moreover, Monte Carlo simulations were performed to assess the practical performance of the proposed design, revealing that no failures occurred during any operations.