Phaser: Phased methodology for modeling the system-level effects of soft errors

被引：0
|
作者：
IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, United States [1 ]
不详 [2 ]
不详 [3 ]
机构：
来源：
IBM Journal of Research and Development | 2008年 / 52卷 / 03期
关键词：
This paper presents all overview of Phaser; a toolset and methodology for modeling the effects of sqft errors on the architectural and microarchitectural functionality of a system. The Phaser framework is used to understand the system-level effects of soft-error rates of a microprocessor chip as its design evolves through the phases of preconcept; concept; high-level design; and register-transfer-level design implementation. Phaser represents a strategic research vision that is being proposed as a next-generation toolset for predicting chip-level failure rates and studying reliability-performance tradeoffs during the phased design process. This paper primarily presents Phaser/ M1; the early stage of the predictive modeling of behavior. © Copyright 2008 by International Business Machines Corporation;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Journal article (JA)
引用
收藏
页码：293 / 306
相关论文
共 50 条
  • [1] Phaser: Phased methodology for modeling the system-level effects of soft errors
    Rivers, Jude A.
    Bose, Pradip
    Kudva, Prabhakar
    Wellman, John-David
    Sanda, Pia N.
    Cannon, Ethan H.
    Alves, Luiz C.
    IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2008, 52 (03) : 293 - 306
  • [2] System-Level Effects of Soft Errors in Uncore Components
    Cho, Hyungmin
    Cheng, Eric
    Shepherd, Thomas
    Cher, Chen-Yong
    Mitra, Subhasish
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 36 (09) : 1497 - 1510
  • [3] Characterizing System-Level Masking Effects against Soft Errors
    Ko, Yohan
    ELECTRONICS, 2021, 10 (18)
  • [4] Capacitor Modeling Methodology for System-level ESD Simulation
    Li Xiang
    Xie Xiaofei
    Xia Nan
    Gu Zhengdong
    2019 IEEE 26TH INTERNATIONAL SYMPOSIUM ON PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2019,
  • [5] A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems
    Shazli, Syed Z.
    Abdul-Aziz, Mohammed
    Tahoori, Mehdi B.
    Kaeli, David R.
    2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2008, : 621 - 630
  • [6] Characterizing System-Level Vulnerability for Instruction Caches against Soft Errors
    Wang, Shuai
    2011 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2011, : 356 - 363
  • [7] Thermal Modeling Methodology for Efficient System-Level Thermal Analysis
    Santos, Cristiano
    Vivet, Pascal
    Matter, Gene
    Peltier, Nicolas
    Kaiser, Sylvian
    Reis, Ricardo
    2014 IEEE PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2014,
  • [8] Enhanced IC Modeling Methodology for System-level ESD Simulation
    Xiong, Jie
    Chen, Zaichen
    Xiu, Yang
    Mu, Zhen
    Raginsky, Maxim
    Rosenbaum, Elyse
    2018 40TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD), 2018,
  • [9] System-level modeling and validation increase design productivity and save errors
    Chown, Bill
    2005 International Symposium on System-On-Chip, Proceedings, 2005, : 7 - 7
  • [10] System-Level Hardware-Based Protection of Memories against Soft-Errors
    Gherman, Valentin
    Evain, Samuel
    Cartron, Mickael
    Seymour, Nathaniel
    Bonhomme, Yannick
    DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3, 2009, : 1222 - 1225
12345