A new design methodology of low power asynchronous comparator

被引：0
|
作者：
Jiang, Xiao-Bo [1 ]
Ye, De-Sheng [1 ]
机构：
[1] School of Electronic and Information Engineering, South China University of Technology, Guangzhou, Guangdong 510641, China
来源：
Tien Tzu Hsueh Pao/Acta Electronica Sinica | 2012年 / 40卷 / 08期
关键词：
D O I：
10.3969/j.issn.0372-2112.2012.08.024
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：1650 / 1654
相关论文
共 50 条
  • [1] Asynchronous design methodology for an efficient implementation of low power ALU
    Manikandan, P.
    Liu, B. D.
    Chiou, L. Y.
    Sundar, G.
    Mandal, C. R.
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 590 - +
  • [2] Design of Low Power Magnitude Comparator
    Gupta, Akash
    Khatri, Manohar
    Rajput, Sachin Kumar
    Mehra, Anu
    Bathla, Shikha
    PROCEEDINGS OF THE 7TH INTERNATIONAL CONFERENCE ON CLOUD COMPUTING, DATA SCIENCE AND ENGINEERING (CONFLUENCE 2017), 2017, : 754 - 758
  • [3] Design of Compact and Low Power Reversible Comparator
    Nayak, V. Shiva Prasad
    Prasad, Govind
    Chowdary, K. Dedeepya
    Chari, K. Manjunatha
    2015 INTERNATIONAL CONFERENCE ON CONTROL, INSTRUMENTATION, COMMUNICATION AND COMPUTATIONAL TECHNOLOGIES (ICCICCT), 2015, : 17 - 21
  • [4] The design of a low power asynchronous multiplier
    Liu, YJ
    Furber, S
    ISLPED '04: PROCEEDINGS OF THE 2004 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2004, : 301 - 306
  • [5] Asynchronous design and the pursuit of low power
    Athas, B
    SEVENTH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 2001, : 2 - 2
  • [6] A new methodology for the design of asynchronous digital circuits
    Nanda, K
    Desai, SK
    Roy, SK
    TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 342 - 347
  • [7] TAST profiler and low energy asynchronous design methodology
    Slimani, K
    Rémond, Y
    Sicard, G
    Renaudin, M
    INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2004, 3254 : 268 - +
  • [8] Design of efficient Double Tail Comparator for Low Power
    Chaudhari, Siddharth
    Pawar, Mahesh
    2015 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2015, : 1782 - 1785
  • [9] A New Design Optimization Methodology of Fully Differential Dynamic Comparator
    Khanfir, Leila
    Mouine, Jaouhar
    INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS, 2023, 53 (02):
  • [10] Low Power Asynchronous Circuit Design Methodology using a new Single Gate Sleep Convention Logic (SG-SCL)
    Lee, Jin Kyung
    Kim, Kyung Ki
    2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2017, : 317 - 320
12345