Design of energy-efficient full subtractor circuit at near threshold computing for signal processing application

Energy Efficiency is a critical factor while designing integrated circuits. Therefore, a 1-bit full subtractor (FS) cell is proposed for lower power application by employing Gate Level Body Biasing (GLBB) scheme for Near Threshold Computing (NTC) application to conquer a unique module for achieving full swing borrow output.We evaluate power, delay, energy and the product of energy with delay (EDP) metrics with respect to C-CMOS full subtractor. The proposed feedback based with FS with GLBB technique has a total die area of 60.02 mu m2, while the average power, delay, and energy are 1138 pW, 242 ns, and 27.53 aJ, respectively. The results revealed that our proposed subthreshold hybrid FS circuit with GLBB scheme successfully achieved more than 10.46% average power consumption, 26.58% energy consumption reductions, and 17.98% EDP savings compared to conventional CMOS configuration and other hybrid counterparts. GLBB circuits with FS achieve performance levels that are not affordable in C-CMOS, DTMOS,and GLBB with full adder configurations. Therefore, the FS circuit serves as an efficient divider circuit in terms of detecting objects for image processing applications.