A 3D photon-to-digital converter readout for low-power and large-area applications

被引:1
|
作者
Rossignol, T. [1 ]
Roy, N. [1 ]
Parent, S. [1 ]
Deslandes, K. [1 ]
Nolet, F. [1 ]
Charlebois, S. A. [1 ]
Pratte, J. -F. [1 ]
机构
[1] Univ Sherbrooke, Interdisciplinary Inst Technol Innovat, 3000 Blvd Univ, Sherbrooke, PQ, Canada
来源
JOURNAL OF INSTRUMENTATION | 2024年 / 19卷 / 09期
基金
加拿大自然科学与工程研究理事会; 加拿大创新基金会;
关键词
Digital electronic circuits; Electronic detector readout concepts (gas; liquid); Front-end electronics for detector readout; VLSI circuits; CMOS; PHOTOMULTIPLIERS;
D O I
10.1088/1748-0221/19/09/P09017
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
A new trend in large area noble liquid experiments is to measure the scintillation light with photodetectors and their electronics inside the active volume. Compared to the typical approach of using silicon photomultipliers (SiPM) with an analog readout chain leading to an analog-to-digital converter, this paper presents a new 3D photon-to-digital converter (PDC) readout that takes advantage of the binary nature of the single-photon avalanche diodes (SPAD). The readout contains 4096 pixels over 25 mm2, 2 , each including a 3D bonding pad and a quenching circuit. The readout features three different outputs: a fast flag to get the timestamp of each event from an external time-to-digital converter, a digital sum to retrieve the number of pixels triggered during an event, and an analog monitor to generate an analog SiPM-like output. The analog monitor is also used to validate the two former digital outputs. The readout also includes 61 2D CMOS SPADs for validation purpose prior to the final 3D integration with SPADs custom made according to our design by Teledyne DALSA (Bromont, Canada). As a first system integration toward large-area detector applications, a mini-tile of 2 x 2 readouts has been developed to test all the functionalities. The measured single-photon timing resolution ranges from 72 to 93 ps FWHM across the mini-tile SPAD channels population (i.e. 4 x 61 channels). The flag timing resolution is below 95 ps RMS, which includes the contribution of the optimized flag H-tree but also an additional trigger tree that replaces the 3D SPAD array at this stage of development. Once bonded with the 3D SPADs, the trigger tree won't be required to measure the flag timing resolution. With the removed contribution of the trigger tree, the estimated flag timing resolution should be below 45 ps RMS. The extent of the benefits of the digital sum output depend on the application, and this paper focuses on two cases. First, a low-power coincidence scheme such as required by the nEXO liquid xenon experiment, leading to a power consumption as low as 140 mu W per PDC. With a finer sampling of the scintillation light such as required for pulse shape discrimination in liquid argon, the power consumption remains below 100 mu W per PDC. Overall, this readout is designed as a replacement for a typical analog SiPM chain, without compromise on the performances.
引用
收藏
页数:20
相关论文
共 50 条
  • [21] Low-power 3D integrated ferromagnetic computing
    Becherer, M.
    Breitkreutz, S.
    Eichwald, I.
    Ziemys, G.
    Kiermaier, J.
    Csaba, G.
    Schmitt-Landsiedel, D.
    2015 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), 2015, : 121 - 124
  • [22] LOW-POWER 3-BIT PIEZOELECTRIC MEMS ANALOG TO DIGITAL CONVERTER
    Proie, Robert
    Pulskamp, Jeffrey S.
    Polcawich, Ronald G.
    Ivanov, Tony
    Zaghloul, Mona
    2011 IEEE 24TH INTERNATIONAL CONFERENCE ON MICRO ELECTRO MECHANICAL SYSTEMS (MEMS), 2011, : 1241 - 1244
  • [23] Low-Power 3D Integration using Inductive Coupling Links for Neurotechnology Applications
    Fletcher, Benjamin J.
    Das, Shidhartha
    Poon, Chi-Sang
    Mak, Terrence
    PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2018, : 1211 - 1216
  • [24] LArPix: demonstration of low-power 3D pixelated charge readout for liquid argon time projection chambers
    Dwyer, D. A.
    Garcia-Sciveres, M.
    Gnani, D.
    Grace, C.
    Kohn, S.
    Kramer, M.
    Krieger, A.
    Lin, C. J.
    Luk, K. B.
    Madigan, P.
    Marshall, C.
    Steiner, H.
    Stezelberger, T.
    JOURNAL OF INSTRUMENTATION, 2018, 13
  • [25] Formation of large-area stretchable 3D graphene-nickel particle foams and their sensor applications
    Yang, Cheng
    Xu, Yuanyuan
    Man, Peihong
    Zhang, Hao
    Huo, Yanyan
    Yang, Chuanxi
    Li, Zhen
    Jiang, Shouzhen
    Man, Baoyuan
    RSC ADVANCES, 2017, 7 (56): : 35016 - 35026
  • [26] 3D floorplanning of low-power and area-efficient Network-on-Chip architecture
    Xue, Licheng
    Shi, Feng
    Ji, Weixing
    Khan, Haroon-Ur-Rashid
    MICROPROCESSORS AND MICROSYSTEMS, 2011, 35 (05) : 484 - 495
  • [27] Large-Area Super-Resolution 3D Digital Maps for Indoor and Outdoor Wireless Channel Modeling
    Zhang, Qianyu
    Niu, Guanchong
    Pun, Man-On
    2018 IEEE 87TH VEHICULAR TECHNOLOGY CONFERENCE (VTC SPRING), 2018,
  • [28] A compact low-power algorithmic A/D converter implemented on a large scale FPAA chip
    Tzu-Yun Wang
    Sheng-Yu Peng
    Jennifer Hasler
    Analog Integrated Circuits and Signal Processing, 2018, 94 : 65 - 74
  • [29] A compact low-power algorithmic A/D converter implemented on a large scale FPAA chip
    Wang, Tzu-Yun
    Peng, Sheng-Yu
    Hasler, Jennifer
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2018, 94 (01) : 65 - 74
  • [30] Design of a low-power Digital-to-Pulse Converter (DPC) for in-memory-computing applications
    Humood, Khaled
    Pan, Yihan
    Wang, Shiwei
    Serb, Alexander
    Prodromakis, Themis
    MICROELECTRONICS JOURNAL, 2024, 153