Architecture and implementation of an application specific instruction set for multimedia and communication

An application specific instruction set for multimedia and communication was introduced. A unified DSP plus general-purpose CPU processor based on this instruction set was designed and implemented. The CPU instruction set was compatible with the MIPS 4KC instruction set and the DSP instruction set was designed independently by analyzing the characteristic of the application. This paper presented the instructions and their operation logic in detail. The proposed instructions are suitable for 'pixel', 'vector' and 'complex' operations according to the high parallelism of the application. The test results have shown that the instruction set presented has obvious advantage in some multimedia and communication arithmetic, such as image interpolation, reconstruction and filter and FFT. The chip test result has shown that this architecture is feasible.