Performance explorations of multi-core network on chip router

被引：0
|
作者：
Saravanakumar, U. [1 ]
Rangarajan, R. [2 ]
机构：
[1] Department of Electronics and Communication Engineering, PSG College of Technology, Coimbatore, India
[2] Department of Electronics and Communication Engineering, Indus College of Engineering, Coimbatore, India
来源：
International Journal of Simulation: Systems, Science and Technology | 2012年 / 13卷 / 01期
关键词：
Energy utilization - Servers - Field programmable gate arrays (FPGA) - Routers - Distributed computer systems - Programmable logic controllers - Computer architecture - Network architecture;
D O I：
10.5013/IJSSST.a.13.01.04
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：36 / 42
相关论文
共 50 条
  • [1] A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems
    Poluri, Pavan
    Louri, Ahmed
    IEEE COMPUTER ARCHITECTURE LETTERS, 2015, 14 (02) : 107 - 110
  • [2] A FAST MULTI-CORE VIRTUAL PLATFORM FOR PERFORMANCE EVALUATION OF NETWORK ON CHIP
    Ma, Xichao
    Zhou, Haijie
    Wang, Zongyan
    Yu, Zhiyi
    Zeng, Xiaoyang
    2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
  • [3] Some initial explorations into the hierarchical multi-core chip design space for HPC systems
    Kogge, Peter M.
    INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS, 2007, : 3 - 10
  • [4] Wireless Network-on-Chip: A New Era in Multi-Core Chip Design
    Deb, Sujay
    Mondal, Hemanta Kumar
    PROCEEDINGS OF THE 2014 25TH IEEE INTERNATIONAL SYMPOSIUM ON RAPID SYSTEM PROTOTYPING (RSP): SHORTENING THE PATH FROM SPECIFICATION TO PROTOTYPE, 2014, : 59 - 64
  • [5] Reliable network-on-chip design for multi-core system-on-chip
    Kuei-Chung Chang
    The Journal of Supercomputing, 2011, 55 : 86 - 102
  • [6] Reliable network-on-chip design for multi-core system-on-chip
    Chang, Kuei-Chung
    JOURNAL OF SUPERCOMPUTING, 2011, 55 (01): : 86 - 102
  • [7] New on-chip interconnection network for multi-core processor
    Qiao, Bao-Jun
    Shi, Feng
    Ji, Wei-Xing
    Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology, 2007, 27 (06): : 511 - 516
  • [8] A Survey on Performance of On-Chip Cache for Multi-core Architectures
    Priya, B. Krishna
    Joshi, Amit D.
    Ramasubramanian, N.
    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON INFORMATICS AND ANALYTICS (ICIA' 16), 2016,
  • [9] Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip
    Kritikos, WilliamV.
    Schmidt, Andrew G.
    Sass, Ron
    Anderson, Erik K.
    French, Matthew
    INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING, 2012, 2012
  • [10] Multi-core Image Processing System using Network on Chip Interconnect
    Joshi, Jonathan
    Karandikar, Kedar
    Bade, Sharad
    Bodke, Mandar
    Adyanthaya, Rohan
    Ahirwal, Balkrishan
    2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 2007, : 1011 - +
12345