Hardware implementation of multi-objective differential evolution algorithm: A case study of spectrum allocation in cognitive radio networks

被引:0
|
作者
Anumandla K.K. [1 ]
Peesapati R. [2 ]
Sabat S.L. [3 ]
机构
[1] Department of Electrical Engineering, Indian Institute of Technology Hyderabad, Hyderabad
[2] Department of Electronics and Communication Engineering, National Institute of Technology Meghalaya, Shillong, Meghalaya
[3] Centre for Advanced Studies in Electronics Science and Technology, University of Hyderabad, Telangana
来源
Anumandla, Kiran Kumar (ee17pdf02@iith.ac.in) | 1600年 / Inderscience Publishers, 29, route de Pre-Bois, Case Postale 856, CH-1215 Geneva 15, CH-1215, Switzerland卷 / 08期
关键词
Auxiliary processor unit; Cognitive radio; FPGA; Hardware accelerator; MODE; Multi-objective differential evolution; Network utility functions; Pareto front; Spectrum allocation; System on chip;
D O I
10.1504/IJICA.2017.088176
中图分类号
学科分类号
摘要
In this paper, a hardware solution for multi-objective differential evolution (MODE) algorithm is presented. The proposed hardware is developed as a co-processor and interfaced with PowerPC440 processor of Virtex-5 field programmable gate array to accelerate execution speed on an embedded platform. It is validated by optimising four standard benchmark functions and its execution time is compared with the same algorithm running on a 32-bit PowerPC440 processor. Further, as a case study, the proposed hardware is used to solve Spectrum Allocation (SA) problem in Cognitive Radio Network (CRN). In CRN, the available licensed channels are assigned to cognitive users using SA task while satisfying the multiple objectives posed by licensed users. The MODE core is integrated with the SA objective functions and developed as a MODE-based SA (MODE-SA) co-processor on an embedded platform for distributed CRN. The MODE-SA core has attained a speedup of 50-60× compared to the PowerPC440 implementation. Copyright © 2017 Inderscience Enterprises Ltd.
引用
收藏
页码:241 / 253
页数:12
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