Coupling capacitance extraction between TSVs in 3D ICs using inverse of inductance Matrix

被引:0
|
作者
Kobayashi, Tetsuya [1 ]
Niioka, Nanako [1 ]
Fukase, Masa-Aki [1 ]
Kurokawa, Atsushi [1 ]
机构
[1] Hirosaki University, 3, Bunkyocho, Hirosaki-shi, Aomori,036-8561, Japan
关键词
Compilation and indexing terms; Copyright 2025 Elsevier Inc;
D O I
10.1541/ieejeiss.135.744
中图分类号
学科分类号
摘要
Inductance - Inverse problems - Matrix algebra - Capacitance - Electronics packaging - Extraction - Timing circuits
引用
收藏
页码:744 / 751
相关论文
共 50 条
  • [21] Challenges in the Reliability of 3D Integration using TSVs
    Stiebing, M.
    Vogel, D.
    Steller, W.
    Wolf, M. J.
    Wunderle, B.
    2015 16TH INTERNATIONAL CONFERENCE ON THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME), 2015,
  • [22] High Aspect Ratio TSVs in Micropin-Fin Heat Sinks for 3D ICs
    Dembla, Ashish
    Zhang, Yue
    Bakir, Muhannad S.
    2012 12TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO), 2012,
  • [23] Full-Chip Multiple TSV-to-TSV Coupling Extraction and Optimization in 3D ICs
    Song, Taigon
    Liu, Chang
    Peng, Yarui
    Lim, Sung Kyu
    2013 50TH ACM / EDAC / IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2013,
  • [24] A study on substrate noise coupling among TSVs in 3D chip stack
    Araga, Yuuki
    Nagata, Makoto
    De Vos, Joeri
    Van der Plas, Geert
    Beyne, Eric
    IEICE ELECTRONICS EXPRESS, 2018, 15 (13):
  • [25] Coupling Capacitance in Face-to-Face (F2F) Bonded 3D ICs: Trends and Implications
    Song, Taigon
    Nieuwoudt, Arthur
    Yu, Yun Seop
    Lim, Sung Kyu
    2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 529 - 536
  • [26] A Novel Approach for Using TSVs As Membrane Capacitance in Neuromorphic 3-D IC
    Ehsan, M. Amimul
    An, Hongyu
    Zhou, Zhen
    Yi, Yang
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (08) : 1640 - 1653
  • [27] The Accelerated 3D Capacitance Extraction Based on Adaptive Low-Rank Matrix Factorization
    Huang J.
    Feng X.
    Yu W.
    Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics, 2022, 34 (07): : 1138 - 1146
  • [28] Design Quality Tradeoff Studies for 3D ICs Built with Nano-scale TSVs and Devices
    Yang, Kaiyuan
    Kim, Dae Hyun
    Lim, Sung Kyu
    2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED), 2012, : 740 - 746
  • [29] Equivalent Circuit Model Extraction for Interconnects in 3D ICs
    Engin, A. Ege
    2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2013, : 1 - 6
  • [30] Towards Automatic Thermal Network Extraction in 3D ICs
    Li, Mingyu
    Khasanvis, Santosh
    Shi, Jiajun
    Bhat, Sachin
    Rahman, Mostafizur
    Moritz, Csaba Andras
    PROCEEDINGS OF THE 2016 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH), 2016, : 25 - 30