共 50 条
- [1] A PLL with variable loop gain for fast lock-in ISIC-99: 8TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, DEVICES & SYSTEMS, PROCEEDINGS, 1999, : 263 - 266
- [2] Design of a Fast Lock-in IC for CP-PLL Dianzi Keji Daxue Xuebao/Journal of the University of Electronic Science and Technology of China, 2021, 50 (02): : 180 - 185
- [3] A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 1525 - 1528
- [4] A new phase-locked loop with enhanced lock-in design WSEAS Trans. Circuits Syst., 2006, 8 (1323-1328):
- [5] A Fast-Lock PLL with Over-tuning Control 2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 970 - 972
- [6] Lock-in time characteristics of dual delay lock loop ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 1997, 80 (06): : 93 - 102
- [8] An Fast Lock Technique for Wide Band PLL Frequency Synthesizer Design 2014 INTERNATIONAL CONFERENCE ON INFORMATION SCIENCE, ELECTRONICS AND ELECTRICAL ENGINEERING (ISEEE), VOLS 1-3, 2014, : 763 - 767
- [9] Design of low noise and fast lock PLL by using switch matrix 2012 10TH INTERNATIONAL SYMPOSIUM ON ANTENNAS, PROPAGATION & EM THEORY (ISAPE), 2012, : 1181 - 1183
- [10] Lock-in time characteristics of double correlator delay lock loop ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 2002, 85 (02): : 43 - 51