Low-cost FPGA-based multi-channel TDC with high resolution and density for time-of-flight detectors

被引:0
|
作者
Wang, Xinpeng [1 ,2 ]
Yang, Haibo [1 ,3 ]
Xia, Xiaolin [1 ,3 ]
Zou, Chaojie [1 ,3 ]
Su, Yangzhou [1 ,3 ]
Sun, Wenchao [1 ,3 ]
Wang, Shikai [1 ,2 ]
Zhao, Yun [2 ]
Zhao, Chengxin [1 ,3 ]
机构
[1] Chinese Acad Sci, Inst Modern Phys, Lanzhou 730000, Peoples R China
[2] Northwest Normal Univ, Coll Phys & Elect Engn, Lanzhou 730070, Peoples R China
[3] Univ Chinese Acad Sci, Sch Nucl Sci & Technol, Beijing 100049, Peoples R China
来源
JOURNAL OF INSTRUMENTATION | 2024年 / 19卷 / 11期
基金
中国国家自然科学基金;
关键词
Digital electronic circuits; Digital signal processing (DSP); Front-end electronics for detector readout;
D O I
10.1088/1748-0221/19/11/C11008
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
The Time-to-Digital Converter (TDC) is widely used for precise time interval measurements and play a critical role in Time-of-Flight (ToF) applications. In this paper, we present the design of a 64-channel leading-edge and trailing-edge TDC based on a Field-Programmable Gate Array (FPGA). This TDC is implemented on a Xilinx Kintex-7 XC7K410T-2FFG900I FPGA and consists of modules including a coarse counter, pulse generator, tapped delay line, decomposition encoder, and calibrator. To better evaluate its performance, we designed a multi-channel hardware verification board. According to laboratory test results, the timing precision has a root mean square (RMS) value of 6.69 ps, and a least significant bit (LSB) of 2.99 ps. The experimental results confirm that our TDC design achieves excellent timing precision.
引用
收藏
页数:10
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