Research on key techniques in BIST implementation of logic core

被引：0
|
作者：
Li, Ji
Xu, Yongjun
Han, Yinhe
Li, Xiaowei
机构：
[1] Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
[2] Graduate School, Chinese Academy of Sciences, Beijing 100039, China
来源：
Jisuanji Gongcheng/Computer Engineering | 2005年 / 31卷 / 23期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：55 / 57
相关论文
共 50 条
  • [41] Design and Implementation of Boundary Scan Testing of Core Logic on FPGA
    Srinivas, Seema
    Sheshagiri, H. N.
    2017 2ND IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2017, : 327 - 331
  • [42] Characteristic faults and spectral information for logic BIST
    Chen, XD
    Hsiao, MS
    IEEE/ACM INTERNATIONAL CONFERENCE ON CAD-02, DIGEST OF TECHNICAL PAPERS, 2002, : 294 - 298
  • [43] Deterministic logic BIST for transition fault testing
    Gherman, V.
    Wunderlich, H.-J.
    Schloeffel, J.
    Garbers, M.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2007, 1 (03): : 180 - 186
  • [44] A programmable BIST core for embedded DRAM
    Huang, CT
    Huang, JR
    Wu, CF
    Wu, CW
    Chang, TY
    IEEE DESIGN & TEST OF COMPUTERS, 1999, 16 (01): : 59 - 70
  • [45] Scan-based ATPG or logic BIST?
    Williams, TW
    INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, : 1183 - 1183
  • [46] Optimizing BIST and Repair Logic for Embedded Memories
    Karunaratne, Maddumage
    Oomann, Bejoy
    2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2008, : 350 - +
  • [47] Efficient pattern mapping for deterministic logic BIST
    Gherman, V
    Wunderlich, HJ
    Vranken, H
    Hapke, F
    Wittke, M
    Garbers, M
    INTERNATIONAL TEST CONFERENCE 2004, PROCEEDINGS, 2004, : 48 - 56
  • [48] Circuit partitioning for efficient logic BIST synthesis
    Irion, A
    Kiefer, G
    Vranken, H
    Wunderlich, HJ
    DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 86 - 91
  • [49] An enhanced logic BIST architecture for Online testing
    Yang, F.
    Chakravarty, S.
    Devta-Prasanna, N.
    Reddy, S. M.
    Pomeranz, I.
    14TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS, 2008, : 10 - 15
  • [50] Application of Deterministic Logic BIST on Industrial Circuits
    Gundolf Kiefer
    Harald Vranken
    Erik Jan Marinissen
    Hans-Joachim Wunderlich
    Journal of Electronic Testing, 2001, 17 : 351 - 362
12345