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- [1] Effective Fault Isolation using Memory BIST and Logic BIST Diagnostic Techniques ISTFA 2011: CONFERENCE PROCEEDINGS FROM THE 37TH INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS, 2011, : 176 - 181
- [2] An effort-minimized logic BIST implementation method INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, : 1002 - 1010
- [3] Practical Challenges in Logic BIST Implementation - Case Studies PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 2008, : 265 - 265
- [4] A BIST Logic Design for MarchS3C Memory Test BIST Implementation ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY, 2009, 12 (04): : 440 - 454
- [5] Logic BIST and scan test techniques for multiple identical blocks 20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2002, : 60 - 65
- [6] Key techniques in research and implementation of the direct quadrature conversion transceiver CHINESE JOURNAL OF ELECTRONICS, 2004, 13 (04): : 738 - 742
- [7] Research and Implementation of Key Techniques for Indoor Movement Object Trajectory Prediction 2018 THE 9TH ASIA CONFERENCE ON MECHANICAL AND AEROSPACE ENGINEERING, 2019, 1215
- [8] Design and Implementation of BIST 2018 3RD INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, COMMUNICATION, COMPUTER, AND OPTIMIZATION TECHNIQUES (ICEECCOT - 2018), 2018, : 1142 - 1146
- [9] Logic BIST architecture for FPGAs PROCEEDINGS OF THE 44TH IEEE 2001 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2001, : 442 - 445
- [10] A BIST scheme for asynchronous logic SEVENTH ASIAN TEST SYMPOSIUM (ATS'98), PROCEEDINGS, 1998, : 27 - 32