共 50 条
- [1] MULTI-ALGORITHM TARGETED LOW MEMORY BANDWIDTH ARCHITECTURE FOR H.264/AVC INTEGER-PEL MOTION ESTIMATION 2008 IEEE INTERNATIONAL CONFERENCE ON MULTIMEDIA AND EXPO, VOLS 1-4, 2008, : 701 - 704
- [4] High parallel-pipeline integer-pel and fractional-pel motion estimation VLSI architectures for H.264/AVC VLSI CIRCUITS AND SYSTEMS III, 2007, 6590
- [5] A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 848 - 851
- [6] Hardware dedicated integer-pel motion estimator for high definition H.264/AVC video encoder 2008 DIGEST OF TECHNICAL PAPERS INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, 2008, : 311 - 312
- [7] Integer-pel Motion Estimation Specific Instructions and their Hardware Architecture for ASIP 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 953 - 956
- [9] Hybrid algorithm with adaptive complexity for integer PEL motion estimation of H.264 2005 IEEE International Conference on Multimedia and Expo (ICME), Vols 1 and 2, 2005, : 101 - 104
- [10] Level D data reuse integer motion estimation VLSI architecture for H.264/AVC Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2007, 35 (10): : 1921 - 1926