Fully-depleted SOI CMOS devices and circuits

被引：0

作者：

Sun, Hai-Feng ^{[1
]}

Liu, Xin-Yu ^{[1
]}

Hai, Chao-He ^{[1
]}

机构：

[1] R and D Cent. of Microelectron., Chinese Acad. of Sci., Beijing 100029, China

来源：

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors | 2001年 / 22卷 / 07期

关键词：

Circuit theory - Electric breakdown - Polysilicon - Semiconductor devices - Threshold voltage;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

CMOS transistors are fabricated on fully-depleted, ultrathin (70nm) Silicon-on-Insulator (SOI) films. NMOS devices have a P+-polysilicon gate, while PMOS devices have an N+-polysilicon gate. It makes the threshold voltage close to 0.7V with a light channel doping. A new technique i.e., preamorphization implantation (PAI) with heavy ions of germanium(Ge), is applied to 0.8μm CMOS/SOI devices in order to reduce the series resistance in the source and drain regions so as to prevent the voids from forming. In this way, the sheet resistance of the silicided SOI layer approximates 5.2Ω/. The minimum ring-oscillator delay was measured as 45ps per stage.

引用

页码：947 / 950

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