Power and Area Efficient 9T CNTFET SRAM Bit Cells with Differential Read Scheme for Low Power Applications

Design of VLSI circuits using CMOS technology in the deep submicron range come across many issues like increased leakage power and process variations. Therefore, as an alternative Carbon Nano Tube Field Effect Transistor (CNTFET) is explored for nanoscale range circuits. CNTFET offers high stability, high performance and consumes low power. Low voltage operation and noise tolerant SRAM bit cells have become much essential due to their great usage in low power applications which mainly includes the Bio medical devices. Memory banks with low power are much important since 70% of the die area is surrounded by them. This paper presents two different CNTFET based SRAM bits of 9 transistors using Differential Read Scheme. These designs achieve enhancement in stability and reduction in power with reduced area occupancy. The designs are implemented in Cadence using CNTFET 32nm technology operated at 900mv. © School of Science, IHU. All rights reserved.