Design and Implementation of Integration Padding Reconfigurable Hash Algorithm Circuit

被引：0
|
作者：
Chen T. [1 ]
Lian Y. [1 ]
Li W. [1 ]
Nan L. [1 ]
机构：
[1] College of Cryptography Engineering, Information Engineering University, Zhengzhou
来源：
Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology | 2021年 / 41卷 / 06期
关键词：
Hash algorithm; Padding; Reconfigurable; Reuse;
D O I：
10.15918/j.tbit1001-0645.2020.105
中图分类号：
学科分类号：
摘要：
In view of the lack of filling circuits in the implementation of existing domestic hash algorithms, and the existing designs do not support the SHA3 algorithm standard, a complete circuit was designed to support 11 common hash algorithms in 5 categories, including MD5, SHA1, SM3, SHA2 and SHA3 series. Firstly, analyzing 2 types of filling rules and 6 filling bit widths, the filling process was arranged with different states. Then, considering the characteristics of each arithmetic operation circuit and the reuse of operation unit resources, a reconfigurable operation circuit was designed. Finally, a complete circuit was integrated from algorithm filling to output. Compared with the software filling method under the synthesis of 55nm process library, the performance of SM3, SHA2_384, and SHA2_512 can be improved by 11%, 22% and 22% respectively. © 2021, Editorial Department of Transaction of Beijing Institute of Technology. All right reserved.
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页码：671 / 678
页数：7
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