Difference-equalisation based estimation of timing skew for time-interleaved ADCs in communication systems

被引：0
|
作者：
Li X. [1 ,2 ]
Gao B. [1 ,2 ]
Yan C. [1 ,2 ]
Ding D. [1 ]
Wu J. [1 ,2 ]
机构：
[1] National ASIC System Engineering Research Center, Southeast University, Nanjing
[2] Jiangsu Provincial Key Laboratory of Sensor Network Technology, Southeast University, Nanjing
来源：
Electronics Letters | 2019年 / 55卷 / 25期
基金：
中国国家自然科学基金;
关键词：
Analog to digital conversion - Timing circuits;
D O I：
10.1049/el.2019.2975
中图分类号：
学科分类号：
摘要：
A difference-equalisation based method is presented to estimate timing skew adaptively in time-interleaved analogue-to-digital converters (ADCs). By digital zero-crossing detection and calculating the mean of the absolute difference between adjacent sub-ADC’s outputs, the timing mismatch information for each channel can be identified easily. Simulation results demonstrate that the proposed method can estimate timing skew accurately. Furthermore, the proposed method requires far fewer samples to estimation than the previous methods. © The Institution of Engineering and Technology 2019.
引用
收藏
页码：1326 / 1329
页数：3
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