A trapezoidal cross-section stacked gate FinFET with gate extension for improved gate control

被引:0
|
作者
Mangesh S. [1 ]
Chopra P. [2 ]
Saini K.K. [3 ]
机构
[1] Dr. APJ Abdul Kalam Technical University, Lucknow
[2] Ajay Kumar Garg Engineering College, Ghaziabad
[3] National Physical Laboratories, New Delhi
关键词
Drain induced barrier lowering (DIBL); Gate induced drain leakage (GIDL); Silicon on-insulator (SOI); Subthreshold swing (SS);
D O I
10.14569/IJACSA.2019.0100125
中图分类号
学科分类号
摘要
An improved trapezoidal pile gate bulk FinFET device is implemented with an extension in the gate for enhancing the performance. The novelty in the design is trapezoidal cross-section FinFET with stacked metal gate along with extension on both sides. Such improved device structure with additional process cost exhibits significant enhancement in the performance metrics specially in terms of leakage current behavior. The simulation study proves the suitability of the device for low power applications with improved on/off current ratio, subthreshold swing (SS), drain induced barrier lowering (DIBL), Gate Induced Drain Leakage (GIDL) uniform distribution of electron charge density along the channel and effects of Augur recombination within the channel. © 2018 The Science and Information (SAI) Organization Limited.
引用
收藏
页码:189 / 194
页数:5
相关论文
共 50 条
  • [21] The Impact of Fin/Sidewall/Gate Line Edge Roughness on Trapezoidal Bulk FinFET Devices
    Huang, Wen-Tsung
    Li, Yiming
    2014 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD), 2014, : 281 - 284
  • [22] Gate-overlapped-source Heterojunction Tunnel Tri-gate FinFET
    Kumar, Pankaj
    Roy, Saurav
    Baishya, Srimanta
    PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON 2017 DEVICES FOR INTEGRATED CIRCUIT (DEVIC), 2017, : 561 - 564
  • [23] Stringer Gate FinFET on Bulk Substrate
    Han, Jin-Woo
    Wong, Hiu Yung
    Moon, Dong-Il
    Braga, Nelson
    Meyyappan, M.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (09) : 3432 - 3438
  • [24] Measurement of a cross-section for single-event gate rupture in power MOSFET's
    Mouret, I
    Calvel, P
    Allenspach, M
    Titus, JL
    Wheatley, CF
    LaBel, KA
    Calvet, MC
    Schrimpf, RD
    Galloway, KF
    IEEE ELECTRON DEVICE LETTERS, 1996, 17 (04) : 163 - 165
  • [25] Surface roughness limited mobility in multi-gate FETs with arbitrary cross-section
    Badami, O.
    Lizzit, D.
    Specogna, R.
    Esseni, D.
    2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2016,
  • [26] Critical parameters of gate control in NC-FinFET on GaAs
    Henghui Li
    Tingting Jia
    Chong Zhang
    Ziwei Yu
    Quansheng Guo
    Hongyang Zhao
    Chunyang Jia
    Shuhui Yu
    Rong Sun
    Journal of Computational Electronics, 2023, 22 : 164 - 177
  • [27] Measurement of a cross-section for single-event gate rupture in power MOSFET's
    Univ of Arizona, Tucson, United States
    IEEE Electron Device Lett, 4 (163-165):
  • [28] Critical parameters of gate control in NC-FinFET on GaAs
    Li, Henghui
    Jia, Tingting
    Zhang, Chong
    Yu, Ziwei
    Guo, Quansheng
    Zhao, Hongyang
    Jia, Chunyang
    Yu, Shuhui
    Sun, Rong
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2023, 22 (01) : 164 - 177
  • [29] Double trenches LDMOS with trapezoidal gate
    Yuan, Na
    Wu, Lijuan
    Yang, Hang
    Song, Yue
    Hu, Limin
    Lei, Bing
    Zhang, Yinyan
    MICRO & NANO LETTERS, 2018, 13 (05): : 695 - 698
  • [30] RF Analysis of a Fully Gate Covered Junctionless FinFET for Improved Performance
    Tyagi, Aman
    Mangal, Gaurav
    Chaujar, Rishu
    PROCEEDINGS OF 3RD IEEE CONFERENCE ON VLSI DEVICE, CIRCUIT AND SYSTEM (IEEE VLSI DCS 2022), 2022, : 93 - 97