A General Hardware Trojan Technique Targeted on Lightweight Cryptography with Bit-Serial Structure

被引：0
|
作者：
Yang, Yijun [1 ,2 ]
Wu, Liji [1 ,2 ]
Yuan, Ye [1 ,2 ]
Zhang, Xiangmin [1 ,2 ]
机构：
[1] Institute of Microelectronics, Tsinghua University, Beijing,100084, China
[2] Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing,100084, China
来源：
Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, LNICST | 2019年 / 284卷
关键词：
713.4 Pulse Circuits - 723 Computer Software; Data Handling and Applications;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Hardware security
引用
收藏
页码：647 / 655
相关论文
共 25 条
  • [1] A symmetric differential clock generator for bit-serial hardware
    Myjak, MJ
    Delgado-Frias, JG
    CDES '05: PROCEEDINGS OF THE 2005 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2005, : 159 - 164
  • [2] A Small GIFT-COFB: Lightweight Bit-Serial Architectures
    Caforio, Andrea
    Collins, Daniel
    Banik, Subhadeep
    Regazzoni, Francesco
    PROGRESS IN CRYPTOLOGY - AFRICACRYPT 2022, 2022, 13503 : 53 - 77
  • [3] Bit-serial arithmetic: A novel approach to fuzzy hardware implementation
    Dick, Scott
    Gaudet, Vincent
    Bai, Huiqing
    2008 ANNUAL MEETING OF THE NORTH AMERICAN FUZZY INFORMATION PROCESSING SOCIETY, VOLS 1 AND 2, 2008, : 312 - 317
  • [4] Low Cost Hardware Implementation of LEA-128 Encryption using Bit-Serial Technique
    Choi, Byungjun
    Kim, Bohun
    Park, Jongsun
    2018 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2018, : 46 - 47
  • [5] BIT-SERIAL SYSTOLIC SORTING - GENERAL COMPLEXITIES AND AN IMPLEMENTATION IN VLSI
    LI, HF
    JAYAKUMAR, R
    SUN, X
    IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1987, 134 (03): : 125 - 132
  • [6] A Hardware Implementation of Word-Parallel Bit-Serial Polynomial Basis Multiplier
    Cho, Yong Suk
    Choi, Jae Yeon
    COMPUTER APPLICATIONS FOR GRAPHICS, GRID COMPUTING, AND INDUSTRIAL ENVIRONMENT, 2012, 351 : 176 - +
  • [7] Hardware implementation of an additive bit-serial algorithm for the discrete logarithm modulo 2k
    Li, L
    Fit-Florea, A
    Thomton, MA
    Matula, DW
    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW FRONTIERS IN VLSI DESIGN, 2005, : 130 - 135
  • [8] High Throughput and Hardware Efficient Hybrid LDPC Decoder Using Bit-Serial Stochastic Updating
    Hu, Shuai
    Han, Kaining
    Zhu, Yubin
    Shen, Guodong
    Wang, Fujie
    Hu, Jianhao
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 70 (09) : 3653 - 3664
  • [9] DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching
    Wu, Lingxi
    Sharifi, Rasool
    Venkat, Ashish
    Skadron, Kevin
    IEEE COMPUTER ARCHITECTURE LETTERS, 2022, 21 (02) : 89 - 92
  • [10] A Dedicated Bit-serial Hardware Neuron for Massively-Parallel Neural Networks in Fast Epilepsy Diagnosis
    Kueh, Si Mon
    Kazmierski, Tom
    2017 IEEE-NIH HEALTHCARE INNOVATIONS AND POINT OF CARE TECHNOLOGIES (HI-POCT), 2017, : 105 - 108
123